RISC-V CPU simulator
RISC-V CPU simulator for education purposes
Czech Technical University in Prague
cz.cvut.edu.comparch.qtrvsimRISC-V processor architecture simulator for education purposes with pipeline and cache visualization.
Screenshots
Observed history
| App | Change | Version | When ↑ |
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No observed changes yet.
The initial import establishes a baseline. Future version changes will appear here.
Browse the app catalogue →Upstream releases
Release notes supplied by the developer. These dates are not Flathub package publication times.
0.9.81 Oct 2024
Current project release.
0.9.716 Feb 2024
GUI fix crash when no tab is selected, use bundled LibElf on macOS as Homebrew misses RISC-V
0.9.611 Dec 2023
RISC-V A extension, ACLINT MTIMER, IRQ support, L2 cache, GUI editor tabs
0.9.516 Jan 2023
More CSR updates, fix branch range, CLI OS emulation, coreview diagrams updates, RV64IM in CI